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1 lt1641-1/lt1641-2 164112fc positive high voltage hot swap controllers the lt 1641-1/lt1641-2 are 8-pin hot swap tm control- lers that allow a board to be safely inserted and removedfrom a live backplane. using an external n-channel pass transistor, the board supply voltage can be ramped up at a programmable rate. a high side switch driver controls an n-channel gate for supply voltages ranging from 9v to 80v. the chips feature a programmable analog foldback cur- rent limit circuit. if the chips remain in current limit for more than a programmable time, the n-channel pass transistor is either latched off (lt1641-1) or is set to automatically restart after a time-out delay (lt1641-2). the pwrgd output indicates when the output voltage, sensed by the fb pin, is within tolerance. the on pin provides programmable undervoltage lockout. the lt1641-1/lt1641-2 are available in the 8-lead so package. hot board insertion electronic circuit breaker industrial high side switch/circuit breaker 24v/48v industrial/alarm systems allows safe board insertion and removal from alive backplane controls supply voltage from 9v to 80v programmable analog foldback current limiting high side drive for an external n-channel latched operation mode (lt1641-1) automatic retry (lt1641-2) user programmable supply voltage power-up rate undervoltage lockout overvoltage protection both are available in 8-lead so package *smat70a *diodes, inc. v in 24v short pin gnd v cc timer sense gate d1cmpz 5248b gnd pwrgd pwrgd fb r5 10 ? 5% on r1 49.9k 1% 1641-1 ta01 r2 3.4k 1% c20.68 f r6, 1k, 5% r s 0.01 ? c1 10nf r359k 1% r43.57k 1% r724k 5% c l v out lt1641-1/lt1641-2 q1 irf530 24v input voltage application applicatio s u features typical applicatio u descriptio u , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. downloaded from: http:///
2 lt1641-1/lt1641-2 164112fc supply voltage (v cc ) ............................... 0.3v to 100v input voltage (sense) ............................. 0.3v to 100v input voltage (timer) ............................... 0.3v to 44v input voltage (fb, on) ............................... 0.3v to 60v output voltage (pwrgd) ........................ 0.3v to 100v output voltage (gate) ............................ 0.3v to 100v operating temperature range lt1641-1c, lt1641-2c ........................... 0 c to 70 c lt1641-1i, lt1641-2i ........................ 40 c to 85 c storage temperature range ................. 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c absolute axi u rati gs w ww u package/order i for atio uu w (note 1) the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 24v symbol parameter conditions min typ max units v cc v cc operating range 98 0 v i cc v cc supply current on = 3v 2 5.5 ma v lko v cc undervoltage lockout 7.5 8.3 8.8 v v fbh fb pin high voltage threshold fb low to high transition 1.280 1.313 1.345 v v fbl fb pin low voltage threshold fb high to low transition 1.221 1.233 1.245 v v fbhst fb pin hysteresis voltage 80 mv i infb fb pin input current v fb = gnd 1 a ? v fb fb pin threshold line regulation 9v v cc 80v 0.05 mv/v v sensetrip sense pin trip voltage (v cc ?v sense )v fb = 0v 81 21 7 m v v fb = 1v 39 47 55 mv i gateup gate pin pull-up current charge pump on, v gate = 7v ? 10 20 a i gatedn gate pin pull-down current any fault condition, v gate = 2v 35 70 100 ma ? v gate external n-channel gate drive v gate ?v cc , v cc = 10.8v to 20v 4.5 18 v v cc = 20v to 80v 10 18 v i timerup timer pin pull-up current v timer = 0v 24 80 132 a i timeron timer pin pull-down current v timer = 1v 1.5 3 5 a v onh on pin high threshold on low to high transition 1.280 1.313 1.345 v v onl on pin low threshold on high to low transition 1.221 1.233 1.245 v v onhyst on pin hysteresis 80 mv i inon on pin input current v on = gnd 1 a v ol pwrgd output low voltage i o = 2ma 0.4 v i o = 4ma 2.5 v i oh pwrgd pin leakage current v pwrgd = 80v 10 a dc electrical characteristics t jmax = 125 c, ja = 110 c/w 1641116411i 16412 16412i lt1641-1cs8lt1641-1is8 lt1641-2cs8 lt1641-2is8 12 3 4 87 6 5 top view v cc sensegate timer on fb pwrgd gnd s8 package 8-lead plastic so order part number s8 part marking consult ltc marketing for parts specified with wider operating temperature ranges. order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbflead free part marking: http://www.linear.com/leadfree/ downloaded from: http:///
3 lt1641-1/lt1641-2 164112fc symbol parameter conditions min typ max units t phlon on low to gate low figures 1, 2 6 s t plhon on high to gate high figures 1, 2 1.7 s t phlfb fb low to pwrgd low figures 1, 3 3.2 s t plhfb fb high to pwrgd high figures 1, 3 1.5 s t phlsense (v cc ?sense) high to gate low figures 1, 4 0.5 1 2 s ac electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolutemaximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwisespecified. t a = 25 c, v cc = 24v typical perfor a ce characteristics uw v cc (v) 0 20 40 60 80 100 i cc (ma) 1641-1 g01 3.53.0 2.5 2.0 1.5 1.0 0.5 0 85 c 25 c ?5 c temperature ( c) 50 25 0 25 50 75 100 i cc (ma) 1641-1 g02 3.02.5 2.0 1.5 1.0 0.5 0 48v 24v temperature ( c) 50 25 0 25 50 75 100 fb pin low voltage threshold (v) 1641-1 g03 1.2501.245 1.240 1.235 1.230 1.225 1.220 1.215 1.210 1.205 1.200 v cc = 48v temperature ( c) 50 25 0 25 50 75 100 fb pin high voltage threshold (v) 1641-1 g04 1.3351.330 1.325 1.320 1.315 1.310 1.305 1.300 1.295 1.290 1.285 1.280 v cc = 48v temperature ( c) 50 25 0 25 50 75 100 fb pin hysteresis (v) 1641-1 g05 0.1000.095 0.090 0.085 0.080 0.075 0.070 0.065 0.060 0.055 0.050 0.045 0.040 v cc = 48v temperature ( c) 50 25 0 25 50 75 100 i gate pull up ( a) 1641-1 g06 ?? ? ? ? ?0 ?1 ?2 ?3 v cc = 48v i cc vs v cc i cc vs temperature fb pin low voltage threshold vstemperature fb pin high voltage threshold vs temperature fb pin hysteresis vs temperature i gate pull up vs temperature downloaded from: http:///
4 lt1641-1/lt1641-2 164112fc typical perfor a ce characteristics uw temperature ( c) 50 25 0 25 50 75 100 gate drive (v gate ?v cc ) (v) 1641-1 g07 1615 14 13 12 11 10 98 7 6 v cc = 48v v cc = 10.8v v cc (v) 0 20 40 60 80 gate drive (v gate ?v cc ) (v) 1641-1 g08 1614 12 10 86 t a = 25 c temperature ( c) 50 25 0 25 50 75 100 timer pin pull up current ( a) 1641-1 g09 ?0 ?0 ?0 ?0 ?0 ?0 100 110 v cc = 48v v cc (v) 10 30 50 70 90 timer pin pull up current ( a) 1641-1 g10 1614 12 10 86 t a = 45 c t a = 0 c t a = 25 c t a = 85 c temperature ( c) 50 25 0 25 50 75 100 on pin high voltage threshold (v) 1641-1 g11 1.3351.330 1.325 1.320 1.315 1.310 1.305 1.300 1.295 1.290 1.285 v cc = 48v temperature ( c) 50 25 0 25 50 75 100 on pin low voltage threshold (v) 1641-1 g12 1.2391.237 1.235 1.233 1.231 1.229 1.227 1.225 1.223 v cc = 48v temperature ( c) 50 25 0 25 50 75 100 on pin low voltage hysteresis (v) 1641-1 g13 0.1000.090 0.080 0.070 0.060 0.050 v cc = 48v i load (ma) 10 30 50 70 90 pwrgd v out low (v) 1641-1 g14 2018 16 14 12 10 86 4 2 0 t a = 45 c v cc = 48v t a = 85 c t a = 25 c v feedback (v) 0 0.2 0.4 0.6 0.8 1 sense pin regulation voltage (mv) 1641-1 g15 5045 40 35 30 25 20 15 10 50 v cc = 48v t a = 25 c gate drive vs temperature gate drive vs v cc timer pin pull up current vstemperature timer pin pull up current vs v cc on pin high voltage threshold vstemperature on pin low voltage threshold vstemperature on pin voltage hysteresis vs temperature pwrgd v out low vs i load sense pin regulation voltage vsv feedback downloaded from: http:///
5 lt1641-1/lt1641-2 164112fc pi fu ctio s uuu on (pin 1): the on pin is used to implement undervoltage lockout. when the on pin is pulled below the 1.233v high-to-low threshold voltage, an undervoltage condition is detected and the gate pin is pulled low to turn the mosfet off. when the on pin rises above the 1.313v low-to-high threshold voltage, the mosfet is turned on again. pulsing the on pin low after a current limit fault will reset the fault latch and allow the part to turn back on. fb (pin 2): power good comparator input. it monitors the output voltage with an external resistive divider. when thevoltage on the fb pin is lower than the high-to-low threshold of 1.233v, the pwrgd pin is pulled low and released when the fb pin is pulled above the 1.313v low- to-high threshold. the fb pin also effects foldback current limit (see figure 7 and related discussion). pwrgd (pin 3): open collector output to gnd. the pwrgd pin is pulled low whenever the voltage at the fbpin falls below the high-to-low threshold voltage. it goes into a high impedance state when the voltage on the fb pin exceeds the low-to-high threshold voltage. an external pull-up resistor can pull the pin to a voltage higher or lower than v cc . gnd (pin 4): chip ground. timer (pin 5): timing input. an external timing capacitor at this pin programs the maximum time the part is allowedto remain in current limit. when the part goes into current limit, an 77 a pull-up current source starts to charge the timing capacitor. whenthe voltage on the timer pin reaches 1.233v, the gate pin is pulled low; the pull-up current will be turned off and the capacitor is discharged by a 3 a pull-down current. when the timer pin falls below 0.5v, the gate pin eitherturns on automatically (lt1641-2) or turns on once the on pin is pulsed low to reset the internal fault latch (lt1641-1). if the on pin is not cycled low, the gate pin remains latched off. use no less than 1.5nf for the timing capacitor, c2. gate (pin 6): the high side gate drive for the external n-channel. an internal charge pump guarantees at least10v of gate drive for supply voltages above 20v and 4.5v gate drive for supply voltages between 10.8v and 20v. the rising slope of the voltage at the gate is set by an external capacitor connected from the gate pin to gnd and an internal 10 a pull-up current source from the charge pump output.when the current limit is reached, the gate pin voltage will be adjusted to maintain a constant voltage across the sense resistor while the timer capacitor starts to charge. if the timer pin voltage exceeds 1.233v, the gate pin will be pulled low. the gate pin is pulled to gnd whenever the on pin is pulled low, the v cc supply voltage drops below the 8.3v undervoltage lockout threshold or the timer pin risesabove 1.233v. sense (pin 7): the current limit sense pin. a sense resistor must be placed in the supply path between v cc and sense. the current limit circuit will regulate thevoltage across the sense resistor (v cc ?v sense ) to 47mv when v fb is 0.5v or higher. if v fb drops below 0.5v, the voltage across the sense resistor decreases linearly andstops at 12mv when v fb is 0v. to defeat current limit, short the sense pin to the v cc pin. v cc (pin 8): the positive supply input ranges from 9v to 80v for normal operation. i cc is typically 2ma. an internal undervoltage lockout circuit disables the chip for inputsless than 8.3v. downloaded from: http:///
6 lt1641-1/lt1641-2 164112fc test circuit v cc sense gate timer onfb pwrgd gnd 5k 10nf 24v 1641-1 f01 v + 5v + figure 1 block diagra w + + + + 80 a v p v p logic 1.233v 0.5v 12mv ~ 47mv undervoltage lockout 8.3v v cc gnd 0.5v 1.233v + + 1.233v pwrgd timer 1641-1 bd v cc sense v p gen fb on 3 a gate + charge pump and gate driver ref gen downloaded from: http:///
7 lt1641-1/lt1641-2 164112fc on 1641-1 f02 gate 5v t plhon 1.313v 1v t phlon 1.233v fb 1641-1 f03 pwrgd 1v t plhfb 1.313v 1v t phlfb 1.233v v cc ?sense 1641-1 f04 gate v cc t phlsense 47mv ti i g diagra s w u w figure 2. on to gate timing figure 3. fb to pwrgd timing figure 4. sense to gate timing applicatio s i for atio wu u u hot circuit insertionwhen circuit boards are inserted into a live backplane, the supply bypass capacitors on the boards draw high peak currents from the backplane power bus as they charge up. the transient currents can permanently damage the con- nector pins and glitch the system supply, causing other boards in the system to reset. the chip is designed to turn on a board? supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. the chip also provides undervoltage and overcurrent protection while a power good output signal indicates when the output supply voltage is ready. power-up sequence the power supply on a board is controlled by placing an external n-channel pass transistor (q1) in the power path (figure 5). resistor r s provides current detection and capacitor c1 provides control of the gate slew rate. resistor r6 provides current control loop compensationwhile r5 prevents high frequency oscillations in q1. resistors r1 and r2 provide undervoltage sensing. after the power pins first make contact, transistor q1 is turned off. if the voltage at the on pin exceeds the turn-on threshold voltage, the voltage on the v cc pin exceeds the undervoltage lockout threshold, and the voltage on thetimer pin is less than 1.233v, transistor q1 will be turned on (figure 6). the voltage at the gate pin rises with a slope equal to 10 a/c1 and the supply inrush current is set at i inrush = c l ?10 a/c1. if the voltage across the current sense resistor r s gets too high, the inrush current will then be limited by the internal current limit circuitry whichadjusts the voltage on the gate pin to maintain a constant voltage across the sense resistor. once the voltage at the output has reached its final value, as sensed by resistors r3 and r4, the pwrgd pin goes high. downloaded from: http:///
8 lt1641-1/lt1641-2 164112fc short-circuit protectionthe chip features a programmable foldback current limit with an electronic circuit breaker that protects against short-circuits or excessive supply currents. the current limit is set by placing a sense resistor between v cc (pin 8) and sense (pin 7).to prevent excessive power dissipation in the pass tran- sistor and to prevent voltage spikes on the input supply during short-circuit conditions at the output, the current folds back as a function of the output voltage, which is sensed at the fb pin (figure 7). when the voltage at the fb pin is 0v, the current limit circuit drives the gate pin to force a constant 12mv drop across the sense resistor. as the output voltage at the fb pin increases, the voltage across the sense resistor in- creases until the fb pin reaches 0.5v, at which point the voltage across the sense resistor is held constant at 47mv. the maximum current limit is calculated as: i limit = 47mv/r sense for a 0.025 ? sense resistor, the current limit is set at 1.88a and folds back to 480ma when the output is shortedto ground. the ic also features a variable overcurrent response time.the time required to regulate q1? drain current depends on: q1? input capacitance; gate capacitor c1 and com- pensation resistor r6; and the internal delay from the sense to the gate pin. figure 8 shows the delay from a voltage step at the sense pin until the gate voltage starts falling, as a function of overdrive. timer the timer pin (pin 5) provides a method for program- ming the maximum time the chip is allowed to operate in current limit. when the current limit circuitry is not active, the timer pin is pulled to gnd by a 3 a current source. after the current limit circuit becomes active, an 80 a pull- up current source is connected to the timer pin and thevoltage will rise with a slope equal to 77 a/c timer as long as the current limit circuit remains active. once the desiredmaximum current limit time is set, the capacitor value is: c(nf) = 62 ?t(ms). if the current limit circuit turns off, the timer pin will be discharged to gnd by the 3 a current source. whenever the timer pin reaches 1.233v, either the inter-nal fault latch is set (lt1641-1) or the autorestart latch is set (lt1641-2). the gate pin is immediately pulled to gnd and the timer pin is pulled back to gnd by the 3 a applicatio s i for atio wu u u short pin v cc timer sense gate 876 54 2 1 3 d1cmpz 5248b gnd pwrgd pwrgd fb r5 10 ? 5% on r1 49.9k 1% v in 24v gnd 1641-1 f05 r2 3.4k 1% c20.68 f r6, 1k, 5% r s 0.025 ? c1 10nf r359k 1% r43.57k 1% r724k 5% + c l v out lt1641-1 q1 irf530 figure 5. typical application figure 6. power-up waveforms downloaded from: http:///
9 lt1641-1/lt1641-2 164112fc applicatio s i for atio wu u u figure 8. response time to overcurrent 12mv 0v 0.5v v fb 1641-1 f07 47mv v cc ?v sense figure 7. current limit sense voltage vs feedback pin voltage 50mv 100mv 150mv 200mv 1641-1 f08 12 s 10 s 8 s 6 s 4 s 2 s propagation delay v cc ?v sense current source. when the timer pin falls below 0.5v, thegate pin either turns on automatically (lt1641-2) or once the on pin is pulsed low to reset the internal fault latch (lt1641-1). the waveform in figure 9 shows how the output latches off following a short-circuit. the drop across the sense resis- tor is held at 12mv as the timer ramps up. since the output did not rise bringing fb above 0.5v, the circuit latches off. for figure 9, c t = 100nf. undervoltage and overvoltage detectionthe on pin can be used to detect an undervoltage condi- tion at the power supply input. the on pin is internally connected to an analog comparator with 80mv of hyster- esis. if the on pin falls below its threshold voltage (1.233v), the gate pin is pulled low and is held low until on is high again. figure 10 shows an overvoltage detection circuit. when the input voltage exceeds the zener diode? breakdown voltage, d2 turns on and starts to pull the timer pin high. after the timer pin is pulled higher than 1.233v, the fault latch is set and the gate pin is pulled to gnd immediately, turning off transistor q1. the waveforms are shown in figure 11. operation is restored either by interrupting power or by pulsing on low. power good detectionthe chip includes a comparator for monitoring the output voltage. the noninverting input (fb pin) is compared against an internal 1.233v precision reference and exhib- its 80mv hysteresis. the comparator? output (pwrgd pin) is an open collector capable of operating from a pull- up as high as 100v. the pwrgd pin can be used to directly enable/disable a power module with an active high enable input. figure 12 shows how to use the pwrgd pin to control an active low enable input power module. signal inversion is accom- plished by transistor q2 and r7. supply transient protection the ic is 100% tested and guaranteed to be safe from damage with supply voltages up to 100v. however, spikes above 100v may damage the part. during a short-circuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage spikes which could exceed 100v. to minimize the spikes, the power trace parasitic inductance should be minimized by using wider traces or heavier trace plating and a 0.1 f bypass capacitor placed between v cc and gnd. a surge suppressor at the input can also prevent damage fromvoltage surges. downloaded from: http:///
10 lt1641-1/lt1641-2 164112fc short pin v cc timer sense gate 876 54 2 1 3 d1cmpz 5248b gnd pwrgd pwrgd fb r5 10 ? 5% on r1 49.9k 1% v in 24v gnd 1641-1 f10 r2 3.4k 1% c20.68 f d230v 1n5256b r6, 1k, 5% r s 0.025 ? c1 10nf r359k 1% r43.57k 1% r724k 5% + c l v out lt1641-1 q1 irf530 figure 10. overvoltage detection figure 11. overvoltage waveforms applicatio s i for atio wu u u figure 9. short-circuit waveforms gate pin voltagea curve of gate drive vs v cc is shown in figure 13. the gate pin is clamped to a maximum voltage of 18v abovethe input voltage. at minimum input supply voltage of 9v, the minimum gate drive voltage is 4.5v. when the input supply voltage is higher than 20v, the gate drive voltage isat least 10v and a regular n-fet can be used. in applica- tions over a 9v to 24v range, a logic level n-fet must be used with a proper protection zener diode between its gate and source (as d1 shown is figure 5). downloaded from: http:///
11 lt1641-1/lt1641-2 164112fc applicatio s i for atio wu u u v cc timer sense gate 876 54 2 1 3 d1cmpz 5248b gnd pwrgd fb r5 10 ? 5% on r1 294k 1% v in 48v uv = 37v gnd 1641-1 f12 r2 10.2k 1% c20.68 f r6, 1k, 5% r s 0.01 ? c1 10nf r3143k 1% r44.22k 1% r747k 5% + c l 220 f q2 mmbt5551lt1 v out lt1641-1 active low enable module v out v out + v in on/off v in + q1 irf530 short pin figure 12. active low enable module r1 senseresistor, r s 1641-1 f14 r2 v cc sense ongnd lt1641-1 i load i load figure 14. recommended layout for r1, r2 and r s figure 13. gate drive vs supply voltage v cc (v) 8 v gate ?v cc (v) 1816 14 12 10 86 4 2 0 1641-1 f13 13 18 23 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. layout considerationsto achieve accurate current sensing, a kelvin connection is recommended. the minimum trace width for 1oz cop- per foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. 0.03" per amp or wider is recom- mended. note that 1oz copper exhibits a sheet resistance of about 530 ? / . small resistances add up quickly in high current applications. to improve noise immunity, putthe resistor divider to the on pin close to the chip and keep traces to v cc and gnd short. a 0.1 f capacitor from the on pin to gnd also helps reject induced noise. figure 14shows a layout that addresses these issues. downloaded from: http:///
12 lt1641-1/lt1641-2 164112fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2001 lt/lwi 0706 rev c ? printed in usa package descriptio u related parts part number description comments lt1640a negative high voltage hot swap controller controls an n-fet at negative side to 80v ltc1421 dual channel hot swap controller operates two supplies from 3v to 12v and a third to 12v ltc1422 high side drive hot swap controller in so-8 system reset output with programmable delay ltc1643 pci hot swap controller 3.3v, 5v, 12v, 12v supplies for pci bus ltc1642 fault protected hot swap controller operates from 3v to 16.5v, handles surges to 33v lt4250 negative 48v hot swap controller active current limiting for supplies from 20v to 80v s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) so8 0303 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc 1 2 3 4 .150 ?.157 (3.810 ?3.988) note 3 8 7 6 5 .189 ?.197 (4.801 ?5.004) note 3 .228 ?.244 (5.791 ?6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note:1. dimensions in 2. drawing not to scale3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) downloaded from: http:///

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